==============================
 GPCIe ȯåȥ桼
==============================

======================
  1. ѥå
======================

GPCIe ϳ K&F Computing Research ҳȯ PCI Express IP 
桼Ȥ߷פϩ GPCIe Ȥ߹ळȤǡPCI Express 
ȥξܺ٤Ω餺¾ PCI Express ǥХȤΥ󥿥ե
¸Ǥޤ

Υѥåˤϰʲ 3 Ĥβϩޤޤޤ
(٤Ƥβϩ VHDL ɤ󶡤ޤ)

  1) GPCIe Ǿ̳ؤ˰֤桼ϩФƴؤʥ󥿥ե
     Ԥ Host Interface Bridge (HIB)

  2) PCI Express ʤ줿ȥ󥶥ءǡء
    PHY MAC ؤȡξ̤˰֤륢ץꥱ (PCI
    Configuration Register  DMA ȥ) ¸ GPCIe 
    

  3) Altera  FPGA ¢ȥ󥷡и PHY PCS ءPMA  ¸
    PHY

ޤΥѥåˤϡHIB Ѥ󥿥եϩΥե
ǥ (ץϩ) ȡ Linux OS 椹뤿Υեȥ
ޤޤƤޤ

ΥѥåΥե빽ϰʲ̤Ǥ

gpciepkg/
  00readme-j                     -- ܥե롣
  00readme                       -- ܥեαѸǡ
  00license-j                    -- ѥåѵ
  00license                      -- 00license-j αѸǡ
  doc/                           -- 桼ɡ¾ʸ
  hib.vhd                        -- GPCIe Ǿ̳ Host Interface Bridge (HIB)
  gpcie.vhd                      -- GPCIe ΥץꥱءPCI Express ȥ󥶥ءǡءPHY MAC ء
  phy.vhd                        -- Altera  FPGA ¢ȥ󥷡Ѥ PCI Express PHY PCS ءPHY PMA ء
  ifpga_{agx,s2gx}{8,4}.vhd      -- HIB Ѥ󥿥եϩΥץ롣
  synth/                         -- ץϩι˻Ѥե (.qpf, .qsf, .sdc)
  Makefile                       -- ƥץ졼Ȥ hib.vhd, gpcie.vhd, phy.vhd 뤿 makefile
  templates/                     -- VHDL ƥץ졼
  scripts/                       -- HIB ѥեȥδ桼ƥƥ
  include/                       -- HIB 饤֥إåե (Linux )
  lib/                           -- HIB 饤֥ (Linux )
  driver/                        -- HIB ǥХɥ饤Х (Linux )
  hibutil/                       -- HIB 饤֥꥽ (Linux )
  sample/                        -- HIB 饤֥Ѥץꥱץ㡣


ܥ桼 2 Ǥ GPCIe εǽפޤ 3 Ǥ 
GPCIe δŪʻˡˤĤޤǤ HIB  FPGA 
¢ȥ󥷡ФѤȤԤޤ 4 Ǥ GPCIe Τ
٤ʻˡˤĤޤ¢ȥ󥷡Ф˳դ 
PHY åפѤˡ䡢HIB 𤵤 GPCIe 󥸥ľ椹
ˡԤޤ 5 Ǥϼפ VHDL ƥƥξܺ
Ԥޤ

ʤʹߤǤϡեΥѥ̾Ϥ٤ܥѥåΥ롼ȥǥ쥯ȥ 
gpciepkg/ Хѥɽޤ


====================
 2. ǽ
====================

Ǥ GPCIe ΥݡȤƤ뵡ǽ FPGA ǥХϩޤ


б PCI Express ǥХ
-----------------------------------

ɥݥȤȤưޤå롼ȥץ쥯Υ롼
ݡȤȤƤѤǤޤ


б FPGA ǥХ
----------------------

Altera Ҥ FPGA ǥХ Arria GX  Stratix II GX бƤޤ

¢ Gbit ȥ󥷡ФʤǥХ (Cyclone II, III, Stratix II) 
ξˤ PIPE 󥿥եĳդ PHY åפȤ߹碌ƻ
ѤǤ褦߷פƤޤưǧϤʤäƤޤ

-------------------------------------------------------------------------
ӥ      졼        PIPE I/F        Arria GX    StratixII GX
-------------------------------------------------------------------------
Gen1.0
(2.5Gb/s)       x8              128b@125MHz               
                x4              64b@125MHz                
                x1              16b@125MHz                
Gen2.0
(5.0Gb/s)       x8              128b@250MHz     -           
                x4              64b@250MHz      -           
                x1              16b@250MHz      -           
-------------------------------------------------------------------------
:б :бͽ


ϩ
--------

GPCIe βϩ hibgpciephy125  3 ĤΥƥƥ鹽Ƥޤ

ƥƥ hib  GPCIe Ǿ̳ؤ˰֤桼ϩФƴؤ
󥿥ե󶡤ޤ

ƥƥ gpcie  PCI Express ʤ줿ʪ (PHY MAC )
ǡءȥ󥶥ؤȡξ̤˰֤륢ץꥱ
ؤޤץꥱؤˤ PCI Configuration Register  
DMA ȥ餬ޤޤޤ

ƥƥ phy125  FPGA ¢ Gbit ȥ󥷡иʪ (PHY
PCS ءPMA ) ޤդ PHY åפѤˤ 
GPCIe  PIPE 󥿥եľ³ƻѤ뤿ᡢΥƥƥ
ϻѤޤ

  <桼߷פˤϩ>
        |
        | HIB 󥿥ե
        | (GPCIe ȼΥ󥿥ե)
        |
  <ƥƥ hib>
        |
        | ץꥱ󥤥󥿥ե
        | (GPCIe ȼΥ󥿥ե)
        |
  <ƥƥ gpcie>
    ץꥱ (PCI ե졼쥸DMA ȥ)
    ȥ󥶥
    ǡ
    ʪ (PHY MAC )
        |
        | PIPE 󥿥ե
        | (PCI Express ʤ줿󥿥ե)
        |
  <ƥƥ phy> 뤤 <PHY å>
    ʪ (PHY PCS ءPHY PMA )
        |
        | PCI Express ꥢ륤󥿥ե
        | (PCI Express ʤ줿󥿥ե)
        |
   PCI Express ǥХ


====================
 3. Ūʻˡ
====================

Ǥ GPCIe δŪʻˡˤĤޤǤ HIB  
FPGA ¢ȥ󥷡ФѤȤԤޤ

桼߷פˤϩ (ʹߥХåɲϩȸƤӤޤ)  GPCIe 
Ѥˤϡƥƥ hib 򥤥󥹥󥷥ȤޤХå
ϩ HIB 󥿥ե̤ƥۥȷ׻ (Τˤ PCI Express 
󥯤ξή˰֤ǥХ) Ȥδ֤ǥǡžԤޤ
HIB  PCI Express ץȥˤǡžȡHIB 󥿥ե
𤷤ǡžȤ֥åޤ

                  PCI Express        HIB 󥿥ե
  ۥȷ׻  <-------------> HIB <------------------> Хåɲϩ

ۥȷ׻  HIB ؤž Programm I/O (PIO) ˤ write ˤ
ƹԤޤHIB Υۥȷ׻ؤž Direct Memory Access
(DMA) ˤ write ˤäƹԤޤܥѥåˤϤž
 Linux ѥեȥ (ǥХɥ饤Фȥ桼饤֥) 
ޤޤƤޤեȥλˡˤĤƤϸҤޤ

Хåɤ HIB Ȥž hib_we, hib_data, backend_we,
backend_data  4 οȡ125MHz Υå clk_out Ѥƹ
ޤХåɤ HIB ؤžϡХåɤΥɥ饤֤ 
write  backend_we ȡƱǡ backend_data ǹԤ
ޤHIB ХåɤؤžϡHIB Υɥ饤֤ write  
hib_we ȡƱǡ hib_data ǹԤޤ

  Хåɤ HIB ؤν񤭹:
    clk_out       __~~__~~__~~__~~__~~__~~__~~
    backend_we    ______~~~~~~~~~~~~~~~~______
    backend_data        <d0><d1><d2><d3>

  HIB Хåɤؤν񤭹:
    clk_out       __~~__~~__~~__~~__~~__~~__~~
    hib_we        ______~~~~~~~~~~~~~~~~______
    hib_data            <d0><d1><d2><d3>

Хåɤ HIB ν񤭹ߤԤ뤳ȤϤǤޤhib_we  
assert Ƥ֤ϡ˥ǡ³ʤƤϤʤޤ

HIB ϥХåɤν񤭹ߤ뤿ΥХåե˻ä
ޤۥȷ׻ DMA write ׵᤬ȡHIB ϤΥХåե
Ƥۥȷ׻ write ޤHIB ȤϥХåեΥСե
åԤޤΤǡХåɤХåեĶǡ
write ˤϡХåɤ񤭹ߥߥ󥰤Ԥɬפ
ޤХåեΥϥǥեȤǤ 1k word (x4 Ǥ 8k byte
x8 Ǥ 16k byte) ꤵƤޤ

HIB ˤ DMA ϩ PIO write ϩإۥȷ׻
饢뤿Υ쥸ʤɤƤޤ
쥸ؤ BAR0 ֤𤷤ƥޤPIO write ϡBAR2 
֤ФƹԤޤPIO write  BAR2  write combined ꤷƻ
ȹ⤤ž®٤褦߷פƤޤܺ٤ˤĤƤϥ
 templates/hibctl.vhd 򻲾ȤƤ

HIB 桼ϩΥץ뤬 ./ifpga_{agx,s2gx}{8,4}.vhd
ˤޤʹߤǤϤΥץϩˡϩιˡȥۥ
׻ˡˤĤޤ


----------
ϩι
----------

ˤ QuartusII ѤޤʳΥġǤιϳǧƤޤ

QuartusII Υץȥե (.qpf) ե (.qsf) Υץ뤬

  ./synth/ifpga_{agx,s2gx}{8,4}.qpf
  ./synth/ifpga_{agx,s2gx}{8,4}.qsf

ˤޤѤҤΥץϩ

  ./ifpga_{agx,s2gx}{8,4}.vhd 

ȡKFCR ɾܡ AGX8, S2GX8 ưϩޤ

ʤɬפ VHDL ե

  ./hib.vhd
  ./ifpga_{agx,s2gx}{8,4}.vhd

 2 եΤߤǤHIB Ū GPCIe  FPGA ¢ Gbit ȥ󥷡
ФѤƤޤ餬ɬפȤ륽 (gpcie.vhd,
phy.vhd)  hib.vhd 礵Ƥ뤿ᡢˤ gpcie.vhd,
phy.vhd ɬפޤ


------------------------
ۥȷ׻
------------------------

ܥѥåˤϡHIB ۥȷ׻椹뤿Υեȥ
ޤƤޤեȥϥǥХɥ饤Фȥ桼饤֥꤫鹽
ƤޤΥեȥ Linux OS ưޤ

Linux ʳ OS ΥեȥϸߤΤȤѥåˤϴޤޤ
ޤ󡣤ϡHIB ϩ߷פ Linux OS ˰¸Ƥ뤳Ȥ
̣ΤǤϤޤŬڤʥեȥȯСLinux ʳ
 OS  HIB 椹뤳ȤǽǤ

ǤϥեȥΥ󥹥ȡ롢ꡢˡˤĤޤ


եȥΥ󥹥ȡ
--------------------------

եȥΥ󥹥ȡ ./scripts/install.csh ¹Ԥλؼ
˽äƲ

  kawai@localhost[1]>./scripts/install.csh
  -----------------------------------------------
   Host Interface Bridge (HIB) software package
   installation program.
  -----------------------------------------------
  
  How many HIBs are you installing?: 1
  
  Confirm your choice.
    number of HIBs you are installing : 1
  Are they correct? (y/n): y
  
  -------------------------------
  Preparing for installation...
  -------------------------------
  
  (ά)
  
  gcc -O0 -g -I. -I../include -o hibtest hibtest.c hibutil.c -lm
  gcc -O0 -g -I. -I../include -o lsgrape lsgrape.c hibutil.c -lm
  
  done


ʤեȥΥ󥹥ȡˤ Linux ͥδʥĥ꡼
ɬפǤ


ǥХɥ饤Ф
----------------------

ǥХɥ饤ФѤˤϡǥХɥ饤Ф Linux ͥإ
󥯤ɬפޤΤˤ ./driver/ ǥ쥯ȥذư
롼ȸ² make installmodule ¹Ԥޤ

  [root@localhost driver]# make installmodule
  ./install0.csh
  
  -- install module hibdrv --
  hibdrv: 1 HIB(s) found.
  
  rm -f /dev/hibdrv[0-9]
  
  /sbin/insmod -f hibdrv.ko
  mknod /dev/hibdrv0 c 253 0
  
  chgrp wheel /dev/hibdrv0
  
  chmod 666 /dev/hibdrv0
  crw-rw-rw- 1 root wheel 253, 0 Jul  9 12:59 /dev/hibdrv0
  -- done --

ˤä HIB ΥǥХɥ饤 hibdrv  Linux ͥ˥
ޤ ϥۥȷ׻ư뤿ӤɬפǤ

/sbin/lsmod ޥɤ¹ԤνϤ hibdrv ȤޤԤޤ
ƤСǥХɥ饤Ф˥󥯤Ƥޤ

  kawai@localhost[2]>lsmod
  Module                  Size  Used by
  hibdrv                 39608  0
  ...                    ...    ...


ǥХɥ饤Ф򽪤ȡۥȷ׻Υץफ HIB 
إǤ褦ˤʤޤ


ưƥ
----------

./hibutil/hibtest ޥɤѤȡHIB ưƥȤԤޤ
㤨 PCI configuration register ؤ read/write, local register ؤ 
read/writež®٤¬ʤɤǽǤʲ˻򼨤ޤ

hibtest ̵Ǽ¹Ԥȡˡɽޤ

  kawai@localhost[3]>./hibtest
  usage: ./hibtest <test_program_ID>
     0) show contents of config & HIB-local registers [devid]
     1) reset DMA and FIFO [devid]
     2) clear HIB-internal FIFO [devid]
     3) show DMA status [devid]
     4) read config register <addr> [devid]
     5) write config register <addr> <val> [devid]
     6) read HIB local registers mapped to BAR0 <addr> [devid]
     7) write HIB local registers mapped to BAR0 <addr> <val> [devid]
     8) read backend memory space mapped to BAR1 <addr> [devid]
     9) write backend memory space mapped to BAR1 <addr> <val> [devid]
    10) check DMA read/write function <size> <sendfunc> [devid] (host <-> HIB)
    11) measure DMA performance <sendfunc> [devid] (host <-> HIB)
    12) measure DMA write performance [devid] (host <- HIB; bypass internal FIFO)
    13) measure DMA read performance <sendfunc> [devid] (host -> HIB; bypass internal FIFO)
    14) reset backend [devid]
    15) raw PIO r/w & DMA r/w [devid]
    16) measure DMA performance with multiple HIBs <sendfunc>  <# of hibs> (host <-> HIBs internal FIFO)
    17) measure DMA write performance with multiple HIBs <# of hibs> [devid offset] (host <- HIBs; bypass internal FIFO)
    18) measure DMA read performance with multiple HIBs <sendfunc> <# of hibs> [devid offset] (host -> HIBs; bypass internal FIFO)
    19) erase configuration ROM (EPCS64) [devid]
    20) write .rpd to configuration ROM (EPCS64) <rpd-file> [devid]
    21) read configuration ROM ID (0x10:EPCS1 0x12:EPCS4 0x14:EPCS16 0x16:EPCS64) [devid]
    22) set pipeline clock frequency to (PCI-X_bus_freq * N / M) <N> <M> [devid]


hibtest 0 ¹ԤȡHIB  PCI configuration register ƤϤޤ

  kawai@localhost[4]>./hibtest 0
  ## hib0:
  protocol : PCIe
  link width negotiated : x8
              supported : x8
  link speed negotiated : 2.5 Gb/s
             supported  : 2.5 Gb/s
  max payload size negotiated : 128 byte
                   supported  : 256 byte
  max read request size : 256 byte
  
  configuration register:
  0x00000000: 0x0e701b1a
  0x00000004: 0x00100007
  0x00000008: 0xff000001
  0x0000000c: 0x00000008
  0x00000010: 0xdf608008 0xdf608000
  0x00000014: 0xdf610008 0xdf610000
  0x00000018: 0xdf600008 0xdf600000
  0x0000001c: 0x00000000 0x00000000
  0x00000020: 0x00000000
  0x00000024: 0x00000000
  0x00000028: 0x00000000
  0x0000002c: 0x0e701b1a
  0x00000030: 0x00000000
  0x00000034: 0x00000080
  0x00000038: 0x00000000
  0x0000003c: 0x000000ff
  PCI Express Capability Register:
  0x00000080: 0x00110010
  0x00000084: 0x00000001
  0x00000088: 0x00001000
  0x0000008c: 0x00000481
  0x00000090: 0x00810000


hibtest 10 10 1 ¹Ԥȡ롼ץХåžΥƥȤԤޤ
10 * 8 byte Υǡ PIO write ˤäƥۥȷ׻ HIB 
Υǡ򤽤Τޤ DMA write ˤäƲޤǡȲ
ǡ˰פˤ OK 򡢰פʤˤ NG 
Ϥޤ

  kawai@localhost[5]>./hibtest 10 10 1
  
  # check hib[0] DMA read/write (host <-> HIB internal FIFO)
  
  size 10
  
  # hib[0] PIO write, and then DMA write (host <-> HIB internal FIFO)
  clear DMA buf...
  DMA read size: 10 words (80 bytes)
  will dmar...
  
  rbuf[0000]: 0x1111111111111111  wbuf[0000]: 0x1111111111111111
  rbuf[0001]: 0x2222222222222222  wbuf[0001]: 0x2222222222222222
  rbuf[0002]: 0x3333333333333333  wbuf[0002]: 0x3333333333333333
  rbuf[0003]: 0x4444444444444444  wbuf[0003]: 0x4444444444444444
  rbuf[0004]: 0x5555555555555555  wbuf[0004]: 0x5555555555555555
  rbuf[0005]: 0x6666666666666666  wbuf[0005]: 0x6666666666666666
  rbuf[0006]: 0x123456789abc0006  wbuf[0006]: 0x123456789abc0006
  rbuf[0007]: 0x123456789abc0007  wbuf[0007]: 0x123456789abc0007
  rbuf[0008]: 0x123456789abc0008  wbuf[0008]: 0x123456789abc0008
  rbuf[0009]: 0x123456789abc0009  wbuf[0009]: 0x123456789abc0009
  ---- transfer size reached ----
  rbuf[0010]: 0x123456789abc000a  wbuf[0010]: 0xfedcba987654000a
  rbuf[0011]: 0x123456789abc000b  wbuf[0011]: 0xfedcba987654000b
  done
   10 words (80 bytes).
  OK

hibtest 12 ¹Ԥ DMA write ž (HIB ۥȷ׻ؤ 
write) ®٤¬Ǥޤ

  kawai@localhost[6]>./hibtest 12
  
  # hib[0] DMA write (host <- HIB)
  size: 1024 DMA write: 1.562367 sec  512.043597 MB/s
  size: 2048 DMA write: 1.101087 sec  726.554697 MB/s
  size: 4096 DMA write: 0.857353 sec  933.104598 MB/s
  size: 8192 DMA write: 0.739353 sec  1082.027209 MB/s
  size: 16384 DMA write: 0.680854 sec  1174.995203 MB/s
  size: 32768 DMA write: 0.651100 sec  1228.690060 MB/s

hibtest 13 1 ¹Ԥ PIO write ž (ۥȷ׻ HIB ؤ 
write) ®٤¬Ǥޤ

  kawai@localhost[7]>./hibtest 13 1
  
  # hib[0] PIO write (host -> HIB)
  size: 64 PIO write: 2.037641 sec  392.610858 MB/s
  size: 128 PIO write: 1.233335 sec  648.647763 MB/s
  size: 256 PIO write: 0.822831 sec  972.253211 MB/s
  size: 512 PIO write: 0.639186 sec  1251.591587 MB/s
  size: 1024 PIO write: 0.620417 sec  1289.455073 MB/s
  size: 2048 PIO write: 0.620460 sec  1289.365885 MB/s
  size: 4096 PIO write: 0.620398 sec  1289.495211 MB/s
  size: 8192 PIO write: 0.620425 sec  1289.438721 MB/s
  size: 16384 PIO write: 0.620416 sec  1289.457550 MB/s

hibtest Ѥ¾ΥƥȤˤĤƤϥ
./hibutil/hibtest.c 򻲾ȤƤ



MTRR 
-----------

ۥȷ׻ HIB ؤΥǡžϡPCI ɥ쥹 BAR2 Ф 
PIO write ˤäƹԤޤԡǽ˶ᤤž®٤ˤϡBAR2 
֤ write combining ⡼ɤꤹɬפޤꤷʤ
ǤžϹԤޤԡǽ 20% 뤤Ϥʲž®٤
ޤ

BAR2 ֤ write combining ⡼ɤꤹˤϡ롼ȸ²ǥ
ץ ./scripts/setmtrr.csh ¹Ԥޤ

  [root@localhost driver]# ./setmtrr.csh
  
  Searching for HIB(s)... Found 0 PCI-X HIB(s). Found 1 PCIe HIB(s).
  Found 1 HIB(s) in total.
  
  Trying to set 1 MTRR(s)...
      echo "base=0xdf600000 size=0x1000 type=write-combining" > /proc/mtrr
  Done.
  
  current setting of MTRRs:
  reg00: base=0x00000000 (   0MB), size=2048MB: write-back, count=1
  reg01: base=0x80000000 (2048MB), size=1024MB: write-back, count=1
  reg02: base=0x100000000 (4096MB), size=200704MB: write-back, count=1
  reg03: base=0x200000000 (8192MB), size=1024MB: write-back, count=1
  reg04: base=0xdf600000 (3574MB), size=   4KB: write-combining, count=1

ץȤνϤ "base=0xAAAAAAAA (XXXXMB), size = 4kB:
write-combining" Ȥʸ󤬴ޤޤƤСԤƤ
 AAAAAAAA  HIB  BAR2 ֤Ƭɥ쥹Ǥͤ
hibtest ޥɤ 4 18 ͿƼ¹Ԥ뤳ȤǳǧǤޤ

  kawai@localhost[8]>../hibutil/hibtest 4 18
  hib[0] config 0x00000018: 0xdf600008

ۥȷ׻ˤäƤ MTRR ǤʤȤޤ (
 4GB ʾܤƤ䡢CPU λ 8 Ĥ٤Ƥ MTRR ¾ PCI 
ǥХˤäƴ˻ѤƤʤ)BIOS ѹˤäƤ
Ǥ礬ޤˡϥåץåȤޥܡ
˰¸ޤΤǡ˴ؤ򻲾ȤƤ

MTRR  hibtest 13 1 Ѥ PIO write ž®٤¬Ԥ
ȡ®٤θǧǤޤ

  MTRR  (8 졼)

  kawai@localhost[9]>./hibtest 13 1
  
  # hib[0] PIO write (host -> HIB)
  size: 64 PIO write: 7.319836 sec  109.292068 MB/s
  size: 128 PIO write: 6.857664 sec  116.657799 MB/s
  size: 256 PIO write: 6.597888 sec  121.250922 MB/s
  size: 512 PIO write: 6.458101 sec  123.875423 MB/s
  size: 1024 PIO write: 6.404411 sec  124.913905 MB/s
  size: 2048 PIO write: 6.397210 sec  125.054514 MB/s
  size: 4096 PIO write: 6.387041 sec  125.253617 MB/s
  size: 8192 PIO write: 6.390173 sec  125.192230 MB/s
  size: 16384 PIO write: 6.384816 sec  125.297269 MB/s


  MTRR  (8 졼)

  kawai@localhost[10]>./hibtest 13 1
  
  # hib[0] PIO write (host -> HIB)
  size: 64 PIO write: 2.037641 sec  392.610858 MB/s
  size: 128 PIO write: 1.233335 sec  648.647763 MB/s
  size: 256 PIO write: 0.822831 sec  972.253211 MB/s
  size: 512 PIO write: 0.639186 sec  1251.591587 MB/s
  size: 1024 PIO write: 0.620417 sec  1289.455073 MB/s
  size: 2048 PIO write: 0.620460 sec  1289.365885 MB/s
  size: 4096 PIO write: 0.620398 sec  1289.495211 MB/s
  size: 8192 PIO write: 0.620425 sec  1289.438721 MB/s
  size: 16384 PIO write: 0.620416 sec  1289.457550 MB/s


桼饤֥λˡ
--------------------------

桼饤֥ϥ桼ץФ HIB Ѥ API 󶡤
桼饤֥Ѥˤϡ桼ץ.
/include/hibutil.h 򥤥󥯥롼ɤ¸ե˥饤֥ 
./lib/libhib.a 󥯤Ƥ

桼饤֥󶡤 API ΤפʤΤʲޤ
̵ API ˤĤƤ ./hibutil/hibutil.[hc] 򻲾ȤƤ

    Hib* hib_openMC(int devid)
      ̻ devid  HIB λѸ¤ޤѸ¤¾Υ
      ˤäƼƤˤϡ¤ޤǥ֥å
      ޤ

      devid  HIB ϩȤͿ뾮Ǥۥȷ׻ 
      n Ĥ HIB 󥹥ȡ뤵Ƥˤϡ줾 HIB ˼
      ̻ 0  n-1 Ƥޤ

      hib_openMC()  Hib ¤ΤؤΥݥ󥿤֤ޤ
      ι¤Τˤ HIB ˴ؤ󤬤ޤȤƤꡢɬפ˱¾
       API Ѥޤ (cf. hib_dmawMC)

    void hib_closeMC(int devid)
      ̻ devid  HIB λѸ¤˴ޤѸ¤˴
       HIB ϡ¾ΥץѤǤ褦ˤʤޤ

    void hib_piowMC(int devid, int size, UINT64 *buf)
      ̻ devid  HIB Фơbuf ǥݥȤ륢ɥ쥹
      Ϥޤ(size * 8) byte ˳ǼƤǡ񤭹ߤޤ
      buf ˤϥ桼־Ū˳ݤ䡢malloc() Ѥ
      ưŪ˳ݤΰʤɡ̾ΥΰǤޤ

    void hib_start_dmawMC(int devid, int size, UINT64 *buf)
      ̻ devid  HIB Фơbuf ǥݥȤ륢ɥ
      Ϥޤ (size * 8) byte إǡ񤭹褦׵ᤷޤ

      ǡbuf ˤǤդΥΰꤹ뤳ȤϤǤʤ
      Ƥbuf ȤƻǤΤ h->dmaw_buf뤤 
      h->dmaw_buf ˥եåȤä h->dmaw_buf + offset ΤߤǤ
      ޤ offset + size ͤ 32k byte Ķ뤳ȤϤǤޤ
       h  hib_openMC() ֤ Hib ¤ΤؤΥݥ󥿤Ǥ
      h->dmaw_buf  Linux Υͥ˳ݤ줿 32k byte Ϣ
      ³ΰ򡢥桼֤إޥåפΤǤ

      ̾Υΰ (桼־Ū˳ݤ䡢malloc() 
      ʤѤưŪ˳ݤΰ)  HIB äǡǼ
      뤿ˤϡä HIB  h->dmaw_buf إǡꡢ
      򥳥ԡƤ

    int hib_finish_dmawMC(int devid)
      hib_start_dmawMC() ȯԤ񤭹׵νλԤޤ

    UINT32 hib_config_readMC(int devid, UINT32 addr)
      ̻ devid  HIB ΡPCI Configuration Register ɥ쥹 
      addr Ϥͤɤ߽Фޤ

    void hib_config_writeMC(int devid, UINT32 addr, UINT32 value)
      ̻ devid  HIB ΡPCI Configuration Register ɥ쥹 
      addr Ϥ value 񤭹ߤޤ

    UINT32 hib_mem_readMC(int devid, UINT32 addr)
      ̻ devid  HIB ΡLocal Register ɥ쥹 
      addr Ϥͤɤ߽ФޤLocal Register Υɥ쥹ޥåפˤ
      Ƥ ./templates/hibctl.vhd 򻲾ȤƤ

    void hib_mem_writeMC(int devid, UINT32 addr, UINT32 value)
      ̻ devid  HIB ΡLocal Register ɥ쥹 
      addr Ϥ value 񤭹ߤޤ


桼饤֥Ѥץꥱץ㤬 
./sample/loopback.c ˤޤΥץϥ롼ץХåžΥƥ
ȤԤޤ10 * 8 byte Υǡ PIO write ˤäƥۥȷ׻
 HIB Υǡ򤽤Τޤ DMA write ˤäƲޤ
ǡȲǡ˰פˤ OK 򡢰פʤ
ˤ NG Ϥޤ

  kawai@localhost[9]>./loopback
  0x0000  sent : 0x123456789abc0000    received : 0x123456789abc0000  OK
  0x0001  sent : 0x123456789abc0001    received : 0x123456789abc0001  OK
  0x0002  sent : 0x123456789abc0002    received : 0x123456789abc0002  OK
  0x0003  sent : 0x123456789abc0003    received : 0x123456789abc0003  OK
  0x0004  sent : 0x123456789abc0004    received : 0x123456789abc0004  OK
  0x0005  sent : 0x123456789abc0005    received : 0x123456789abc0005  OK
  0x0006  sent : 0x123456789abc0006    received : 0x123456789abc0006  OK
  0x0007  sent : 0x123456789abc0007    received : 0x123456789abc0007  OK
  0x0008  sent : 0x123456789abc0008    received : 0x123456789abc0008  OK
  0x0009  sent : 0x123456789abc0009    received : 0x123456789abc0009  OK


======================
 4. ٤ʻˡ
======================

Ǥ GPCIe Τ٤ʻˡˤĤޤ4.1 Ǥϲϩ
ѹˡˤĤޤ4.2 Ǥ¢ȥ󥷡Ф˳
 PHY åפѤˡˤĤޤ4.3 Ǥ HIB 
 GPCIe 󥸥ľ椹ˡˤĤޤ


4.1 ɤΥåץǡ
==============================

GPCIe Υɤ templates/ ǥ쥯ȥ¿Υեʬ
ƵҤƤޤΤƥƥ hib ΰ¸Ƥե
ѾصҤȤĤΥեˤޤȤ᤿Τ hib.vhd Ǥ
Ʊͤˡƥƥ gpcie  phy125 ΰ¸Ƥե򤽤줾
ҤȤĤˤޤȤ᤿Τgpcie.vhd  phy.vhd Ǥ

ɤѹäˤϡgpciepkg Υ롼ȥǥ쥯ȥ 
make ¹ԤƤɤѹ hib.vhdgpcie.vhd
phy.vhdȿǤޤ


4.2 PHY åפλˡ
========================

FPGA ¢Υȥ󥷡Ф˳դ PHY åפѤˤϡ
ƥƥ hib ѹɬפޤ (ƥƥ hib .
/templates/hibtop.vhd Ƥޤ)

ƥƥ hib Ϥ 3 ĤΥƥƥ hibctlgpciephy125 
Υ󥹥󥹤ѤƤޤФ 2 ĤѹɬפǤ

  hib  --+-- hibctl
         |
         +-- gpcie
         |              
         +-- phy125

ޤ󥹥 phy125 ޤ󥹥 phy125 ¢ȥ
Ф PHY PCS ؤ PHY PMA ؤ¸ƤޤפǤΤ
ޤѹˤȤʤphy125  gpcie Ȥδ֤ PIPE 󥿥ե
ˤ³ޤ

˥󥹥 gpcie  PIPE 󥿥ե PHY åפ PIPE 
ե³ޤΤˤ PHY åפ PIPE 󥿥ե
 FPGA  I/O ԥ󤫤ϩκǾ̳ (ץϩѤ
 ./ifpga_{agx,s2gx}{8,4}.vhd Ƥ륨ƥƥ ifpga) 
 port ³ˤ򥨥ƥƥ hib ؤȰɬפ
ޤ


4.3 GPCIe 󥸥ľ椹ˡ
====================================

HIB ϥ桼ϩФƴؤʥ󥿥ե󶡤ޤHIB 
ե GPCIe ΥݡȤ뵡ǽ٤ƤѤ뤳ȤϤǤޤ
㤨аʲεǽѤ뤿ˤϡ桼ϩ HIB 𤵤 GPCIe 
󥸥ľ椹ɬפޤ

  . ɥ쥹Хȥ֥͡롢ȤĤ PIO read/write ž
  . 桼ȼ BAR0BAR5 
  . DMA ͥɲ ( 8 ͥ)

桼ϩ GPCIe 󥸥ľ椹ˤϡgpci.vhd 
Ƥ륨ƥƥ gpcie 桼βϩ˥󥹥󥷥Ȥޤ
FPGA ¢ Gbit ȥ󥷡ФѤˤϡphy.vhd Ƥ
륨ƥƥ phy125 ⥤󥹥󥷥ȤξԤ PIPE 󥿥ե
³ޤ


===================
5. ƥƥܺ
===================

VHDL ƥƥ hibgpciephy125 ¿ generic ѥ᥿ port 
ޤʲǤä˽פ generic ѥ᥿ȡ٤Ƥ port ˤ
ޤ

ʤƥƥ gpcie  generic ѥ᥿ˤϡdefault ͤȤHIB 
˺Ŭ줿ͤꤵƤޤӤ˱ѹƤ

ѥ᥿ˤ PCI Express ǥХȤư
ʤΤ䡢ž®٤˱ƶͿΡϩ񸻤ξ̤˱ƶͿ
Ρϩưȿ˱ƶͿΤޤѥ᥿ΰ̣
򤻤ѹ뤳ȤϤǤޤ


---------------------
ƥƥ hib ܺ
---------------------

entity hib is
  generic (
    DEVICE        : string := "Arria GX"; -- åȤȤ FPGA ǥХ"Arria GX" ⤷ "Stratix II GX" ꤷƤ
    NLANE         : integer               -- PCI Express Υ졼ꤷޤ4 ޤ 8 ꤷƤ
    PIOWBUF_DEPTH : integer := 8;         -- PIO write Хåեοdefault  2^8 word Ǥ
    TXBUF_DEPTH   : integer := 10;        -- backend_data ѥХåեοdefault  2^10 word Ǥ
    USE_CLK32     : integer := 1          -- 0 ꤹ clk32 Ȥʤưߤޤư԰ˤʤǽޤ
                                          -- 餫¤ˤ clk32 򶡵ǤʤˤΤ 0 ꤷƤ
  );
  port (
    phy_linkup    : out std_logic;                             -- PCIe ʪؤ link Ω assert ޤ
    dl_linkup     : out std_logic;                             -- PCIe datalink ؤνλ assert ޤ
    clk32         : in  std_logic;                             -- ȥ󥷡Ф power on reset Υߥ󥰤
                                                               -- ˻Ѥ륯åǤȥ󥷡ФΥ֥졼
                                                               -- ˤѤޤ10MHz-125MHz ǤդμȿοϤƤ

    clk100_ext    : in  std_logic;                             -- Gbit ȥ󥷡ѤΥե󥹥åǤ
                                                               -- 100MHz Υǥե󥷥뿮ϤƤ
    mperst        : in  std_logic;                             -- ꥻåǤ (active low)

    --
    -- PCI Express ꥢ륤󥿥ե
    --
    rx_in         : in  std_logic_vector(NLANE-1 downto 0);    -- PCI Express ®ꥢ뿮μݡȤǤ
    tx_out        : out std_logic_vector(NLANE-1 downto 0);    -- PCI Express ®ꥢ뿮ХݡȤǤ

    wake          : out std_logic;                             -- ̤ѡ
    clk_out       : out std_logic;                             -- PHY PCS ؤ clk100  125MHz 
                                                               -- ѥ륤󥿥եåǤ
                                                               -- HIB Τ٤ƤΥѥ뿮ϤΥåƱޤ
    --
    -- ХåɲϩؤΥ󥿥ե
    --
    hib_we        : out std_logic;                             -- HIB Хåɲϩؤ write ǤοƱ
                                                               -- ǡ hib_data ХåɲϩؽϤޤ
    hib_data      : out std_logic_vector(NLANE*16-1 downto 0); -- HIB ХåɲϩؤΥǡϤǤ
    backend_we    : in  std_logic;                             -- Хåɲϩ HIB ؤ write ǤοƱ
                                                               -- ǡ backend_data  HIB ؽϤޤ
    backend_data  : in  std_logic_vector(NLANE*16-1 downto 0); -- Хåɲϩ HIB ؤΥǡϤǤ
    reset_backend : out std_logic;                             -- ХåɲϩؤΥꥻåȿǤ (active high)
    board_info    : in  std_logic_vector(31 downto 0)          -- ۥȷ׻ɤ߽񤭲ǽʥ᡼ܥå쥸 board_info
                                                               -- νͤͿޤΥ쥸ϥХåɲϩǤդ
                                                               -- Ū˻ѤǤޤ
  );
end hib;


-----------------------
ƥƥ gpcie ܺ
-----------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.gpciepkg.all;  -- gpcie Ѥˤ gpciepkg  use ɬפޤ
                        -- gpciepkg  gpcie.vhd Ƥޤ

entity gpcie is
  generic (
    NLANE             : integer range 1 to 8 := 8; -- PCI Express Υ졼ꤷޤ4 ޤ 8 ꤷƤ
    NDMACH            : integer range 0 to 7 := 2; --  DMA ͥꤷޤ

    MAX_READ_REQ_SIZE : integer := 256; -- max read request size ꤷޤñ̤ byte Ǥ
    MAX_PAYLOAD       : integer := 256; -- βϩǥݡȤ max payload size κͤꤷޤñ̤ byte Ǥ
                                        -- ºݤ̿˻Ѥ max payload size ϾήǥХȤΥͥˤäƷꤵޤ

    CA_PH_VC0_INIT    : integer := 16;  -- Rx Flow Control Хåե (posted, header) οꤷޤñ̤ϥѥåȿǤ
    CA_PD_VC0_INIT    : integer := 64;  -- Rx Flow Control Хåե (posted, data) οꤷޤñ̤ 16byte Ǥ

    CA_NPH_VC0_INIT   : integer := 2;   -- Rx Flow Control Хåե (non-posted, header) οꤷޤñ̤ϥѥåȿǤ
    CA_NPD_VC0_INIT   : integer := 16;  -- Rx Flow Control Хåե (non-posted, data) οꤷޤñ̤ 16byte Ǥ

    CA_CH_VC0_INIT    : integer := 2;   -- Rx Flow Control Хåե (completion, header) οꤷޤñ̤ϥѥåȿǤ
    CA_CD_VC0_INIT    : integer := 16;  -- Rx Flow Control Хåե (completion, data) οꤷޤñ̤ 16byte Ǥ

    CL_PH_VC0_INIT    : integer := 16;  -- Tx Flow Control Хåե (posted, header) οꤷޤñ̤ϥѥåȿǤ
    CL_PD_VC0_INIT    : integer := 64;  -- Tx Flow Control Хåե (posted, data) οꤷޤñ̤ 16byte Ǥ

    CL_NPH_VC0_INIT   : integer := 2;   -- Tx Flow Control Хåե (non-posted, header) οꤷޤñ̤ϥѥåȿǤ
    CL_NPD_VC0_INIT   : integer := 16;  -- Tx Flow Control Хåե (non-posted, data) οꤷޤñ̤ 16byte Ǥ

    CL_CH_VC0_INIT    : integer := 2;   -- Tx Flow Control Хåե (completion, header) οꤷޤñ̤ϥѥåȿǤ
    CL_CD_VC0_INIT    : integer := 16;  -- Tx Flow Control Хåե (completion, data) οꤷޤñ̤ 16byte Ǥ

    CFG_VENDOR_ID_INIT           : std_logic_vector(15 downto 0) := x"1b1a";      -- KFCR ҤΥ٥ ID ǤѹʤǤ (ѵ򻲾)
    CFG_DEVICE_ID_INIT           : std_logic_vector(15 downto 0) := x"0e70";      -- ǥХ ID Ǥ0e70h  KFCR Ҥ HIB ФƳƤǥХ ID Ǥ
    CFG_REVISION_ID_INIT         : std_logic_vector( 7 downto 0) := x"01";        -- ӥ ID Ǥ
    CFG_CLASS_CODE_INIT          : std_logic_vector(23 downto 0) := x"ff0000";    -- PCI 饹ɤǤ

    -- PCI Base Address Register0-5 ȳĥ ROM νͤꤷޤ
    CFG_BAR0_INIT                : std_logic_vector(31 downto 0) := x"ffff8008";  -- 32kB, prefetchable, 32-bit address, memory space.
    CFG_BAR1_INIT                : std_logic_vector(31 downto 0) := x"fffff008";  --  4kB, prefetchable, 32-bit address, memory space.
    CFG_BAR2_INIT                : std_logic_vector(31 downto 0) := x"ffff8008";  -- 32kB, prefetchable, 32-bit address, memory space.
    CFG_BAR3_INIT                : std_logic_vector(31 downto 0) := x"00000000";  -- ̤
    CFG_BAR4_INIT                : std_logic_vector(31 downto 0) := x"00000000";  -- ̤
    CFG_BAR5_INIT                : std_logic_vector(31 downto 0) := x"00000000";  -- ̤
    CFG_BAR_ROM_INIT             : std_logic_vector(31 downto 0) := x"00000000";  -- ̤

    CFG_SUB_VENDOR_ID_INIT       : std_logic_vector(15 downto 0) := x"1b1a";      -- ֥٥ ID Ǥ
    CFG_SUB_DEVICE_ID_INIT       : std_logic_vector(15 downto 0) := x"0e70";      -- ֥ǥХ ID Ǥ
    CFG_INT_PIN_INIT             : std_logic_vector( 7 downto 0) := x"00"         -- Ѥꤷޤ0 ꤷƤ
                                                                                  -- ߤΤȤ GPCIe ϳߤ򥵥ݡȤƤޤ
  );

  port (
    phy_linkup      : out std_logic;  -- ʪؤǥ󥯥ȥ졼˥󥰤λ󥯤Ω assert ޤ
    dl_linkup       : out std_logic;  -- ǡؤνλ̾̿Ԥ֤ܤ assert ޤ
    
    clk             : in  std_logic;  -- PHY PCS ؤ鶡뤵 125MHz Υѥ륤󥿥եåϤޤ
                                      -- PIPE 󥿥եޤह٤ƤΥѥ뿮ϤΥåƱޤ
    rstn            : in  std_logic;  -- ꥻåǤ (active low)

    --
    -- PIPE 󥿥ե
    --
    phystatus       : in  std_logic;
    powerdown       : out std_logic_vector(1 downto 0);
    txdetectrx      : out std_logic;
    txdata          : out std_logic_vector(NLANE*16-1 downto 0);
    txdatak         : out std_logic_vector(NLANE*2-1 downto 0);
    txelecidle      : out std_logic_vector(NLANE-1 downto 0);
    txcompl         : out std_logic_vector(NLANE-1 downto 0);
    rxpolarity      : out std_logic_vector(NLANE-1 downto 0);
    rxdata          : in  std_logic_vector(NLANE*16-1 downto 0);
    rxdatak         : in  std_logic_vector(NLANE*2-1 downto 0);
    rxvalid         : in  std_logic_vector(NLANE-1 downto 0);
    rxelecidle      : in  std_logic_vector(NLANE-1 downto 0);
    rxstatus        : in  std_logic_vector(NLANE*3-1 downto 0);

    --
    -- ץꥱ󥤥󥿥ե
    --

    -- å (졼) read/write 󥿥ե
    slv_readreq     : out std_logic;                             -- read ׵΅Ǥ׵Ф slv_accept  assert  read žϤޤ
    slv_writereq    : out std_logic;                             -- write ׵΅Ǥ׵Ф slv_accept  assert  write žϤޤ
    slv_accept      : in  std_logic;                             -- ĿǤ
    slv_read        : out std_logic;                             -- read ǤομΥåǥ桼ϩ slv_datain إǡϤޤ
    slv_write       : out std_logic;                             -- write ǤοƱƥǡ slv_dataout 桼ϩؽϤޤ
    slv_bar         : out std_logic_vector(6 downto 0);          -- ߥƤ base address ֤򼨤ޤ
    slv_addr        : out std_logic_vector(63 downto 0);         -- ߥƤ륢ɥ쥹򼨤ޤ
    slv_bytevalid   : out std_logic_vector(NLANE*2-1 downto 0);  -- slv_dataout  byte enable Ǥwrite Τ߻Ѥޤ
    slv_bytecount   : out std_logic_vector(11 downto 0);         -- ߤΥȥ󥶥λĤХȿǤ
    slv_dataout     : out std_logic_vector(NLANE*16-1 downto 0); -- GPCIe ΥǡϤǤ
    slv_datain      : in  std_logic_vector(NLANE*16-1 downto 0); -- GPCIe ؤΥǡϤǤ

    -- ˥ (ޥ) read/write 󥿥ե
    ms_wrchannel      : out std_logic_vector(NDMACH-1 downto 0);   --  DMA write Ƥ DMA ͥ򼨤ޤ
    ms_write          : out std_logic;                             -- DMA write ǤομΥåǥ桼ϩ ms_wrdata إǡϤޤ
    ms_wraddr         : out std_logic_vector(31 downto 0);         --  DMA write Ƥ륢ɥ쥹򼨤ޤ
    ms_wrdata         : in  std_logic_vector(NLANE*16-1 downto 0); -- GPCIe ؤ DMA write ǡϤǤ

    ms_rdchannel      : out std_logic_vector(NDMACH-1 downto 0);   --  DMA read Ƥ DMA ͥ򼨤ޤ
    ms_read           : out std_logic;                             -- DMA read ǤοƱƥǡ ms_rddata 桼ϩؽϤޤ
    ms_rdaddr         : out std_logic_vector(31 downto 0);         --  DMA read Ƥ륢ɥ쥹򼨤ޤ
    ms_rddata         : out std_logic_vector(NLANE*16-1 downto 0); -- GPCIe  DMA read ǡϤǤ

    -- DMA ȥ饤󥿥ե
    --    0 ͥ뤫 NDMACH-1 ͥޤǤγ DMA ͥ˰ȤΥ󥿥ե󶡤ޤ
    --     )  n ͥ dma_control  dma_control(n)(6 downto 0) Ǥ
    --   ʤ 2  each7b, each16b, each4b ϥѥå gpciepkg Ƥޤ
    --       
    dma_control       : in  each7b(NDMACH-1 downto 0);             -- DMA 쥸 濮Ǥ
                                                                   --   dma_control(n)(0) : dma_paddrlow_in(n)  write Ǥ
                                                                   --   dma_control(n)(1) : dma_paddrhight_in(n)  write Ǥ
                                                                   --   dma_control(n)(2) : dma_laddr_in(n)  write Ǥ
                                                                   --   dma_control(n)(3) : dma_size_in(n)  write Ǥ
                                                                   --   dma_control(n)(4) : dma_param_in(n)  write Ǥ
                                                                   --   dma_control(n)(5) : 1 åΥѥ륹Ϥ DMA ž򳫻Ϥޤ
                                                                   --   dma_control(n)(6) : 1 åΥѥ륹Ϥ DMA žǤޤ
    dma_param         : in  each16b(NDMACH-1 downto 0);            -- DMA žѥ᥿ꤷޤ
                                                                   --   dma_param(n)(8) : žꤷޤ
                                                                   --                     0:read (ۥȷ׻ɤ߽Ф)  1:write (ۥȷ׻ؤν񤭹)
    dma_status        : out each4b(NDMACH-1 downto 0);             -- DMA žξ֤򼨤ޤ
                                                                   --   dma_status(n)(3) : 0:ž  1:žλ
    dma_fifocnt       : in  each13b(NDMACH-1 downto 0);            -- DMA write  : ѥХåեίäƤǡ byte Ϥޤ
                                                                   -- DMA read   : ѥХåեζ byte Ϥޤ

    dma_paddrlow_in   : in  each32b(NDMACH-1 downto 0);            -- žϥɥ쥹β 32-bit (PCI ɥ쥹) Ϥޤ
    dma_paddrhigh_in  : in  each32b(NDMACH-1 downto 0);            -- žϥɥ쥹ξ 32-bit (PCI ɥ쥹) Ϥޤ
    dma_laddr_in      : in  each32b(NDMACH-1 downto 0);            -- žϥɥ쥹 (륢ɥ쥹) Ϥޤ
    dma_size_in       : in  each32b(NDMACH-1 downto 0);            -- žǡϤޤñ̤ byte Ǥ

    dma_paddrlow_out  : out each32b(NDMACH-1 downto 0);            -- žΥɥ쥹򼨤ޤ (PCI ɥ쥹֡ 32-bit)
    dma_paddrhigh_out : out each32b(NDMACH-1 downto 0);            -- žΥɥ쥹򼨤ޤ (PCI ɥ쥹֡ 32-bit)
    dma_laddr_out     : out each32b(NDMACH-1 downto 0);            -- žΥɥ쥹򼨤ޤ (륢ɥ쥹)
    dma_size_out      : out each32b(NDMACH-1 downto 0)             -- Ĥžǡ򼨤ޤñ̤ byte Ǥ
  );

end gpcie;


------------------------
ƥƥ phy125 ܺ
------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity phy125 is
  generic (
    DEVICE       : string := "Arria GX"; -- åȤȤ FPGA ǥХ"Arria GX" ⤷ "Stratix II GX" ꤷƤ
    NLANE        : integer;              -- PCI Express Υ졼ꤷޤ4 ޤ 8 ꤷƤ
    USE_CLK32    : integer := 1;         -- 0 ꤹ clk32 Ȥʤưߤޤư԰ˤʤǽޤ
                                         -- 餫¤ˤ clk32 򶡵ǤʤˤΤꤷƤ
    SIMULATION   : integer
  );
  port (
    cal_blk_clk             : in    std_logic;    -- ȥ󥷡ФΥ֥졼˻Ѥ륯åǤ
                                                  -- 10MHz-125MHz ǤդμȿοϤƤ
    clk32                   : in    std_logic;    -- ȥ󥷡Ф power on reset Υߥ󥰤뤿˻Ѥ륯åǤ
                                                  -- 10MHz-125MHz ǤդμȿοϤƤ
    clk100                  : in    std_logic;    -- Gbit ȥ󥷡ѤΥե󥹥åǤ
                                                  -- 100MHz Υǥե󥷥뿮ϤƤ
    clk125out               : out   std_logic;    -- PHY PCS ؤ clk100  125MHz Υѥ륤󥿥եåǤ
                                                  -- GPCIe  PIPE 󥿥եޤह٤ƤΥѥ뿮ϤΥåƱޤ
    clk125plllock           : out   std_logic;    -- PLL å졢clk125out ꤷƽϤƤ֤ assert ޤ
    rstn                    : in    std_logic;    -- ꥻåǤ (active low)

    --
    -- PCI Express ꥢ륤󥿥ե
    --
    rx_in                   : in    std_logic_vector(NLANE-1 downto 0);   -- PCI Express ®ꥢ뿮μݡȤǤ
    tx_out                  : out   std_logic_vector(NLANE-1 downto 0);   -- PCI Express ®ꥢ뿮ХݡȤǤ

    --
    -- PIPE 󥿥ե
    --
    wake                    : out   std_logic;
    phystatus               : out   std_logic;
    powerdown               : in    std_logic_vector(1 downto 0);
    txdetectrx              : in    std_logic;
    txdata                  : in    std_logic_vector(NLANE*16-1 downto 0);
    txdatak                 : in    std_logic_vector(NLANE*2-1 downto 0);
    txelecidle              : in    std_logic_vector(NLANE-1 downto 0);
    txcompl                 : in    std_logic_vector(NLANE-1 downto 0);
    rxpolarity              : in    std_logic_vector(NLANE-1 downto 0);
    rxdata                  : out   std_logic_vector(NLANE*16-1 downto 0);
    rxdatak                 : out   std_logic_vector(NLANE*2-1 downto 0);
    rxvalid                 : out   std_logic_vector(NLANE-1 downto 0);
    rxelecidle              : out   std_logic_vector(NLANE-1 downto 0);
    rxstatus                : out   std_logic_vector(NLANE*3-1 downto 0)
  );
end phy125;


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䤤碌ӥХݡȤϲؤꤤޤ:
 K&F Computing Research (support@kfcr.jp)
